1. Field of the Invention
The present invention relates to a memory device, and in particular to a synchronous SRAM circuit.
2. Background of the Related Art
FIG. 1 illustrates a related art synchronous SRAM circuit. As shown in FIG. 1, a cell array 6 includes a plurality of cells each storing a cell data. The plurality of the cells are grouped within a plurality of cell blocks 61 through 64. The following description of the related art SRAM assumes the number of the cell blocks 61 through 64 and the number of column selection signals C/S:n are four (4), respectively.
An address register 1 latches an external address signal Add inputted from the outside in accordance with a clock signal CLK. In accordance with the clock signal CLK, a control register 2 latches various control signals Cout such as read and write signals, and control signals /ADSP, /ADSC, /ADV, which are used for determining the burst mode. A control unit 3 receives control signals /ADSP and /ADSC from the control register 2 and controls corresponding elements.
A counter 4 counts a column selection signal C/S:n inputted from the address register 1 in accordance with a burst mode signal BMS to generate an internal address signal. An address decoder 5 selects one cell among the cells of the cell array 6 and allows a corresponding cell data to be outputted from the selected cell in accordance with the external address signal Add or the internal address signal.
A sense amplifier 7 is formed of a plurality of sense amplifiers 71 through 74. Each of the sense amplifiers 71-74 is connected with a corresponding one of the cell blocks 61 through 64 and receives a cell data for amplification from the corresponding one of the cell blocks 61 through 64. An output register 8 latches a cell data latched by the sense amplifier 7 and outputs the stored cell data to an input and output pad 9 under control of the control unit 3. The data is output to the outside from the input and output pad 9.
In addition, an internal register (not shown) is further provided for inputting a new cell data to the sense amplifier 7 (i.e., a writing operation) under control of the control unit 3. The description of the internal register is omitted.
A cell data reading operation of the related art synchronous SRAM will now be described. An external address signal Add inputted to the address register 1 is latched in accordance with a clock signal CLK and is inputted into the counter 4 and the address decoder 5, respectively. The control signals /ADSP, /ADSC, /ADV inputted into the control register 2 are latched by the control register 2 in accordance with the clock signal CLK.
The control unit 3 determines the level of a control signal CS, which is based on the logic states of the control signals /ADSP, /ADSC, /ADV. The control unit 3 combines the control signals /ADSP and /ADSC to generate a burst mode signal BMS. The counter 4 is enabled by the burst signal BMS and counts the column selection signal C/S:n inputted from the address register 1. As a result, the counter 4 outputs the internal address signal to the address decoder 5.
The address decoder 5 decodes the external address signal or the internal address signal and outputs the decoded signal to the cell array 6. In addition, the address decoder 5 outputs cell block coding signals ANI_I and ANO_I. One block is selected from a plurality of cell blocks 61 through 64. If the counter 4 does not generate the internal address, the address decoder 5 decodes the external address signal Add.
One cell in the cell block is selected in accordance with a decoding signal from the address decoder 5. The cell data stored in the selected cell is amplified by the sense amplifier 7 and is latched by the output register 8. The latched cell data is outputted from the output register 8 to the outside through the input and output pad 9 in accordance with a control signal from the control unit 3.
The method of the related art SRAM for selecting a plurality of cells is determined based on whether the address inputted into the address decoder 5 is the external address or the internal address. When the address decoder 5 operates in accordance with the external address signal Add, the operation of the entire circuit is performed in synchronization with an external clock signal CLK. This is called single read mode. When the address decoder 5 operates in accordance with an internal address signal from the counter 4, the operation of the entire circuit is performed irrespective of the external clock signal. This is called burst read mode.
The single and burst read modes will now be described with reference to FIG. 2 assuming that a number of clock pulses used for implementing a read operation of the related art SRAM is two (2). Namely, it is assumed that the latency is 2. In addition, the description assumes that one data is formed of four cell data, and each cell data is formed of a word unit.
FIG. 2 is a wave form diagram illustrating timing of each element of the related art synchronous SRAM circuit. FIG. 2 illustrates the clock signal CLK, the control signals /ADSP, /ADSC, /ADV, the address signal Add, and data DATA Out. The two control signals /ADSP and /ADSC are used for setting the burst read mode. If both the control signals /ADSP and /ADSC are low level, the entire circuit operates in the burst read mode. According to the timing of FIG. 2, at a time tl where a first clock signal is generated, the mode is the single read mode, and at the time after the time t1, the mode is the burst read mode.
At the time t1 shown in FIG. 2, when the first clock signal is generated, the external address Ao is latched, and the cell data stored in a predetermined cell is read in accordance with the external address Ao. The read cell data Q1(Ao) is latched into the output register 8 through the sense amplifier 7.
At the time t2, if the second clock signal is generated, the cell data Q1(Ao) stored in the output register 8 is outputted to the outside, and the external address signal A1 is latched. At the time t2, the first cell data Q1(Ao) is outputted to the outside, and the second cell data Q1(A1) is latched to the output register 8. Therefore, as described hereinabove, two clock pulses are used until the cell data Q1(Ao) is outputted after an external address is inputted.
At the time t2, the cell data Q1(Ao) stored in the output register 8 is outputted, and at the same time the control signal /ADSC is shifted to a low level. At this time, since the control signal /ADSP is also a low level, the entire circuit begins to operate in the burst read mode. Namely, it is determined whether the mode is the burst read mode at every time tl, t2, t3, . . . at which each clock pulse is generated.
If the control signal /ADV is a low level in the burst read mode, the counter 4 increases the internal address. Namely, the counter 4 counts the column selection signal CS:n. The counted value is inputted into the address decoder 5, and the address decoder 5 outputs a decoded signal for the first cell block 61 of the cell array 6, and the cell data in the interior of the coded cell block 61 is read. The cell data read from the cell block 61 is latched to the output register 8 through the first sense amplifier 71.
If the internal address is increased by the counter 4, the second block 62 of the cell array 6 is coded, and the cell data in the interior of the coded block 62 is read. The cell data read from the cell block 62 is latched to the output register 8 through the second sense amplifier 72. The above-described operation is repeated until the four cell data forming the corresponding data are outputted. Thus, the four cell data Q1(A1), Q2(A1), Q3(A1), Q4(A1) form one data.
The four cell data Q1(A1), Q2(A1), Q3(A1), Q4(A1) are sequentially outputted. To output the four cell data, five clock pulse signals are used. In other words, in the related art SRAM two clock signals are used for outputting one of the cell data. The first clock signal among two clock signals used for outputting the second word (i.e., the second data) shares the second clock signal of the first word. Since the remaining three words are outputted after the first word is outputted, the number of clock signals used for outputting the data formed of the four words is 2+3=5. In addition, the number of the clock signals are the same in the single mode and the burst mode.
In a synchronous SRAM, the data output speed is an important element in determining the system performance. In the related art, another method for increasing the data output speed of an SRAM synchronizes the system to a short period clock signal. However, according to the following articles, the pipeline depth of that SRAM is also increased. See the IEEE Journal of Solid-State Circuits. Vol., 28, No=4,. April, 1993, p48-p489, xe2x80x9cDesign Techniques for High-Throughput BiCMOS Self-Timed SRAMsxe2x80x9d. See also the IEEE Journal of Solid-State Circuits. Vol., 29, No=11, November 1994, p1317-p1312, xe2x80x9cDesign Techniques for High-Throughput BiCMOS Self-Timed SRAMsxe2x80x9d. To increase the pipeline depth, the latency should be increased. Upon increasing the latency, the size of the output register is increased. Accordingly, the area of the circuit for the output register is increased. In this case, the latch register should be located before the sense amplifier, which further requires a very difficult technique.
In addition, for the related art SRAM of FIG. 1, the time required to input the address and store the read data in the output latch through the sense amplifier is more than 65% of the entire access time. These time requirements are illustrated in FIG. 3. Accordingly, the operation speed (frequency) of the related art SRAM or memory chip is determined based on the above-described operations. Therefore, decreasing the operation time shown in FIG. 3 would increase the operation speed of the chip.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to provide a synchronous SRAM circuit that substantially overcomes one or more of the problems caused by disadvantages encountered in the related art.
Another object of the present invention is to provide a memory device circuit that increases an operation speed by allowing the synchronous SRAM to operate at a clock signal having an increased speed or shorter period.
Another object of the present invention is to provide a synchronous SRAM circuit that decreases the time required until a cell data is outputted to the outside through a sense amplifier relative to a given pipeline depth by synchronizing to a fast clock.
Another object of the present invention is to provide a synchronous SRAM circuit outputting data latched to an output register in accordance with a signal having a short clock pulse.
Another object of the present invention is to provide a synchronous SRAM circuit that is capable of latching at one time data having a predetermined number of bits larger than the number of external input and output bits and sequentially outputting the data to the outside using a counter.
Another object of the present invention is to provide a synchronous SRAM that reads a plurality of cell data at one time and sequentially outputs the data.
Another object of the present invention is to provide a synchronous SRAM circuit that operates at a high clock speed by reading a plurality of cell data at a time in a burst read mode and then sequentially outputting a latched data to the outside in accordance with an internal address signal.
To achieve at least the above objects in a whole or in parts, there is provided a synchronous SRAM circuit according to the present invention that includes a control unit outputting a burst mode signal, an address decoder receiving an externally inputted address signal and the burst mode signal, outputting an internal address signal and a block coding signal, a counter enabled by the burst mode signal and counting the block coding signal and outputting a coding signal, and a multiplexer receiving cell data from a plurality of sense amplifier units of a sense amplifier and outputting one cell data among a plurality of the cell data in accordance with the coding signal.
To further achieve the above objects in a whole or in parts, there is provided a circuit for controlling an operation of a cell array formed of a plurality of cells having a matrix form of rows and columns and an output circuit coupled to the cell array to output selected cell data according to the present invention that includes an address decoder that receives an address signal and a burst mode signal and outputs an internal address signal and a block coding signal, a counter enabled by the burst mode signal that counts the block coding signal and outputs a coding signal and a multiplexer that receives a plurality of selected cell data from the output circuit in accordance with the coding signal from the counter and outputs the plurality of selected cell data.
To further achieve the above objects in a whole or in parts, there is provided a memory device according to the present invention that includes a memory array that outputs a plurality of cell data in accordance with a first control signal, a controller that receives an address signal and a mode signal and generates the first control signal and a second control signal and a selector coupled to the memory array that receives the plurality of cell data and outputs the plurality of cell data in accordance with the second control signal.
To further achieve the above objects in a whole or in parts, there is provided a memory device according to the present invention that includes a storage unit formed of a plurality of cells having a matrix form of rows and columns for storing data, an output unit coupled to the storage unit for outputting selected cell data, an address decoding unit for receiving an address signal and a burst mode signal and outputting an internal address signal and a block coding signal, a counter unit for counting the block coding signal and outputting a coding signal, wherein the counter unit is enabled by the burst mode signal and a multiplexer unit for substantially concurrently receiving a plurality of selected cell data from the output circuit in accordance with the coding signal from the counter and outputting the plurality of selected cell data.
To further achieve the above objects in a whole or in parts, there is provided a method of operating a memory device, wherein the memory device includes a cell array formed of a plurality of cells having a matrix form of rows and columns according to the present invention that includes receiving an address signal and a burst mode signal and outputting an internal address signal and a block coding signal to the cell array to select a plurality of cell data, counting the block coding signal and outputting a coding signal, where counting step is initiated by the burst mode signal, sensing the selected plurality of cell data from the cell array and substantially concurrently receiving the plurality of selected cell data from the output circuit in accordance with the coding signal from the counter and outputting the plurality of selected cell data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.